The present invention is directed to a method of attaching a semiconductor integrated circuit active device to a multi-layer ceramic capacitor (MLCC) having a non parallel and a non-uniform surface as compared to the surface of the Integrated Circuit (I/C), and at the same time, creating additional opportunities for increasing functionality of the MLCC assembly.
The proliferation of smaller, more complex, electronic devices is a never ending trend of the electronics industry. Market dynamics have forced circuit designers to achieve more functionality in less space. This has led to a myriad of problems at every level of circuit design starting with the component design, through component attachment techniques, circuit board design, and the design of the device packaging. Design engineers have been forced to develop innovative solutions to increase module functionality without increasing module footprints.
Initially I/C's were connected to a lead frame via a wire bonding process that uses gold wires as the connecting link between the I/C and the lead frame. The lead frame and I/C were then over-molded with epoxy to form a rigid body protecting the I/C from the outside environments. The I/C package was then suitable for assembly onto circuit boards containing additional circuitry and other components. The size of components was not a significant issue in the infancy of the electronics industry. But as size, portability, and increased functionality of electronics became design driving issues, entire assemblies and the components used in them also had to decrease in size.
As the micro electronics industry continues to evolve, more emphasis is being placed on increased functionality fitted into smaller spaces. This trend increases the pressure on packaging, thus forcing the development of new I/C interconnects and packaging technologies that provide continually decreasing foot prints. The ultimate I/C packaging goal is for the package footprint to be no larger than the I/C itself. Towards this goal of miniaturization the I/C has migrated out of the large epoxy over-molded packages and is now frequently mounted directly onto the surface of the circuit board.
The I/C interconnect methods typically include a wire bonding process, as well as other interconnect technologies such as TAB bonding and flip chip bonding. Flip chip bonding technology utilizes small conductive “Bumps” having controlled heights, located on the interconnect pads of the I/C. The chip is flipped face down onto pre-applied solder paste and then soldered directly into position on an electronic circuit board thereby creating an interconnected I/C whose footprint is no larger than the I/C itself. The vertical dimension of the bumps determines the amount of stand-off between the face of the I/C and the substrate to which it is mounted. These bumps can be of different metallurgies generally comprising various solder alloys or gold and having high enough melting points so as not to deform during subsequent attachment or reflow processes. These I/C interconnect technologies have provided design engineers with multiple design options to select from and to pick the best interconnect technology that best satisfies design and performance criteria.
Typically, electronic substrates are relatively flat, <0.010″ deviation per inch of linear length depending on the substrate material. Due to the design of MLCC's, a doming effect can exist on the surface of the MLCC as will be described further herein. This doming effect can be 0.008″ of deviation per inch or even greater over the surface of the MLCC. The doming problem is a particular issue as the size of the MLCC starts to approach the size of the I/C that is to be mounted to the MLCC. Typically wire bonding would be the interconnect technology of choice to interconnect the I/C with the active circuit. However, as the MLCC approaches the size of the I/C, the wire bonds to the MLCC have to be placed near the edge of the MLCC where the maximum amount of rounding occurs. This creates a poor bond and results in lower yields or field reliability issues.
A second issue associated with attaching I/C's directly to the surface of the MLCC is due to the curvature associated with the surface of the MLCC. Since the I/C's are flat by nature, attaching an I/C to a domed surface will leave gaps at the edges of the I/C. It is desirable to create a bond line of uniform thickness between the I/C and the substrate surface to minimize potential Coefficient Thermal Expansion (CTE) issues and also to provide a solid support under the bond pads, located on the face of the I/C, for optimized bonding performance.
Flip Chip bonding of the electronic I/C(s) to the substrate is a potential solution to these two problems. Flip chip attachment enables the footprint area of the electronic chip to be equal to or even larger than the substrate, thereby improving the volumetric functionality of the resulting electronic device.
Flip chip refers to the attachment of a patterned set of conductive three dimensional structures such as ball, stud or other three dimensional structure, fabricated on the bond pads located on the active face of the I/C. These “bumps”, as they are typically referred to, are created during the wafer processing. After the chips have been tested and singulated from the wafer, they are ready for attachment to the circuitry of the circuit board. The electronic chip is then flipped to the “face and bumps down orientation”; the bumps are aligned with corresponding bond pads on the circuit board and then placed into position on the circuit board.
Typically, when a substrate exhibits high amounts of surface curvature, remediation steps must be taken to reduce the surface curvature of the substrate. Such steps may include, but are not limited to, planarization using a surface grinder and polisher, flat firing where the substrate is kept flat using weights or pressure during firing, or other methods used to flatten surfaces. These methods, while at least somewhat effective, are relatively cost prohibitive and are suitable only, for relatively large substrates with a size larger than about 0.25″×0.25″.
There has been a desire for a method for interconnecting one or more substrates with relatively high levels of surface curvature, such as >0.008″ of deviation per linear inch of dimension, to one or more electronic chips, which may or may not have relatively high surface curvature in a manner that is simple and cost effective.